SOC Engineering Intern

Introduction: We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

Internship Experience: At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!

Mission Statement: Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond.

The Team You’ll Be A Part Of:

You'll join a dynamic and highly skilled engineering team focused on delivering world-class ASIC and SoC solutions. The team values collaboration, technical excellence, and continuous learning, working together to solve complex challenges and drive innovation in silicon design. You'll have opportunities to engage with experts across RTL, STA, packaging, and signoff, contributing to a culture of shared knowledge and mutual support.

What You’ll Be Doing:

• Supporting chip-level physical design activities from netlist through final implementation (RTL to GDSII)
• Gaining hands-on experience with key physical design stages, including floorplanning, placement, clock tree synthesis, routing, and physical verification.
• Assisting with design optimization for timing, power, area and congestion 
• Contribute to debugging design or flow issues under guidance from senior engineers
• Supporting the development and improvement of automation scripts and design methodologies. 
• Learning to investigate and troubleshoot design, tool, and flow-related issues throughout the implementation cycle.
• Participating in technical discussions, reviews, and knowledge-sharing activities within the team.

What You’ll Need:

• Currently pursuing a Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
• Basic understanding of digital design, semiconductor fundamentals, and/or ASIC design concepts. 
• Familiarity with the ASIC physical design flow or concepts such as floorplanning, placement, clock tree synthesis, routing, and timing analysis is a plus.
• Basic understanding of timing, power, and physical verification concepts is beneficial. 
• Exposure to EDA tools or physical design tools through coursework, university projects, or previous experience is a plus. 
• Familiarity with scripting or programming languages such as TCL, Python, Perl, or similar is an advantage. 
• Good written and verbal communication skills in English. 
• Eagerness to learn, collaborate, and develop practical engineering skills in a professional environment.

The Impact You Will Have:

• Contributing to the implementation of high-quality ASIC and SoC designs used in advanced technologies. 
• Supporting the team in achieving design performance, power, area, and quality goals. 
• Helping improve design efficiency through automation and methodology enhancements. 
• Contributing to cross-functional collaboration throughout the chip development process. 
• Building practical knowledge of the ASIC physical design flow while working on real engineering challenges. 
• Bring fresh ideas and perspectives while growing your technical skills in a collaborative engineering environment.