Jobs in Karnataka
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IP Design Technical Lead/ Staff ASIC RTL Design Engineer
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13652
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ASIC Digital Design, Staff/ Senior Staff/ Principal Engineer
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 12333
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Analog Design, Staff Engineer
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13534
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SerDes IP Senior Analog Design Engineer
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13506
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Principal Engineer - ASIC Digital Design IP Development (Ethernet/UALink Protocols)
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13479
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Principal ASIC Digital Verification Engineer- IP Development
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13119
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Application Engineering, Sr Engineer
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13515
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Principal Engineer-High Speed Interface Pre-Silicon Validation/Verification
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13115
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Senior Staff Application Engineer - VCS Simulation
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13125
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Director - ASIC Physical Design
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13475
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Staff R&D Engineer - High Performance Core & IPs
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13361
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Senior/Staff Engineer - Product Validation (Prime Time)
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13321
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Sr R&D Engineer (EDA Software)
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13328
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Senior DFT Engineer- Solutions Engineering
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13363
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Principal Engineer-High Speed Interface Pre-Silicon Validation/Verification
Bengaluru, India
Category: Engineering
Posted: 12/16/2025
Job ID: 13245
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Master Thesis internship | Resistor less self-biased current source with dynamic element matching
Porto Salvo, Portugal
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Master Thesis internship | Development of time-domain behavioral model for a ring-oscillator PLL
Porto Salvo, Portugal
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ASIC Digital IP Design/Verification, Director
Dublin, Ireland
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DevOps Intern (Final Semester Student)
Santiago, Chile
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