We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a visionary and experienced leader with a deep understanding of formal verification methodologies and a passion for driving innovation in digital design IPs. With a strong technical background and proven leadership skills, you excel at guiding teams to achieve excellence in verification processes. You understand the complexities of high-speed interface protocols such as CXL, UCIe, USB, and others, and you have a track record of delivering high-quality, reliable IP solutions. Your ability to communicate complex technical concepts clearly and effectively makes you a valuable collaborator with cross-functional teams and external partners. You are committed to fostering a culture of continuous learning, professional growth, and innovation within your team.

What You Will Be Doing:

• Develop and lead the formal verification strategy for IPs, ensuring alignment with industry standards and customer needs for high-speed, high-performance, and reliable IP solutions.
• Oversee the design, execution, and continuous improvement of formal verification methodologies for IPs, including CXL, UCIe, USB, and more.
• Provide technical and strategic guidance to the engineering teams, fostering an environment of collaboration, innovation, and excellence.
• Build and lead a high-performing team of formal verification engineers, defining clear goals, objectives, and metrics for success.
• Mentor and coach engineering managers and technical leads, cultivating technical talent and promoting professional growth within the team.
• Collaborate closely with IP design, architecture, product management, and customer support teams to ensure a seamless and comprehensive verification process.
• Act as the primary technical interface with key clients and partners, presenting verification methodologies, status updates, and final verification results.
• Stay at the forefront of formal verification methodologies and industry trends in IP verification, particularly for high-speed interfaces.
• Represent the company in industry forums, technical conferences, and consortiums, positioning the company as a thought leader in formal verification of high-speed IPs.

The Impact You Will Have:

• Drive the formal verification strategy for cutting-edge digital design IPs, ensuring the delivery of high-quality, reliable IP solutions to leading semiconductor design companies worldwide.
• Enhance the overall quality and performance of IPs through rigorous verification methodologies and continuous improvement processes.
• Foster a culture of innovation and excellence within the engineering teams, leading to the development of industry-leading verification techniques and tools.
• Improve the efficiency and scalability of verification workflows, contributing to the timely and cost-effective delivery of multiple concurrent IP verification projects.
• Strengthen cross-functional collaboration, ensuring a seamless and comprehensive verification process that meets customer requirements and industry standards.
• Position Synopsys as a thought leader in the field of formal verification through active engagement in industry forums, technical conferences, and consortiums.

What You Will Need:

• Bachelors or Master's degree in Electrical Engineering, Computer Engineering, or a related field; a Ph.D. is a plus.
• 10+ years in digital design and formal verification of hardware IPs, with 4+ years in a senior engineering management or director role.
• Proven experience in formal verification methodologies and tools (e.g., Jasper, VC Formal, Questa Formal, etc.).
• Deep understanding of digital design, computer architecture, and high-speed interface protocols such as CXL, UCIe, USB, PCIe, and Ethernet.
• Hands-on experience with verification languages (SystemVerilog Assertions, PSL) and scripting languages (Python, TCL).
• Demonstrated success in leading engineering teams, with a focus on fostering a high-performance culture and enabling team members to grow their technical skills.
• Excellent communication skills, capable of distilling complex technical information into clear, concise presentations for internal stakeholders, partners, and customers.

Who You Are:

• A visionary leader with a passion for innovation and excellence in formal verification.
• A strategic thinker with the ability to develop and implement comprehensive verification strategies.
• A mentor and coach, dedicated to fostering professional growth and continuous learning within your team.
• An effective communicator, able to convey complex technical concepts clearly and concisely.
• A collaborative team player, capable of working closely with cross-functional teams to achieve common goals.
• A thought leader in the field of formal verification, actively engaged in industry forums and technical conferences.

The Team You Will Be A Part Of:

You will be leading a high-performing team of formal verification engineers dedicated to ensuring the quality and reliability of our digital design IPs. This team is responsible for developing and implementing cutting-edge verification methodologies for high-speed interface protocols. You will work closely with IP design, architecture, product management, and customer support teams to deliver high-value IP solutions to leading semiconductor design companies worldwide. Together, you will drive innovation and excellence in formal verification, positioning Synopsys as a leader in the industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.