Principal Engineer - ASIC Digital Design IP Development (Ethernet/UALink Protocols)

Alternate Job Titles:

• Principal Engineer - ASIC Digital Design IP Development (Ethernet/UALink Protocols)

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly experienced and passionate ASIC Digital Design expert with a strong track record in architecting, implementing, and delivering cutting-edge RTL designs for high-performance IP cores. Your expertise spans across protocols such as Ultra Accelerator (UALink), Ethernet, DDR, PCIe, and USB, and you thrive on solving complex technical challenges in fast-paced, multi-site environments. You bring over 12 years of hands-on experience in ASIC design, including control path-oriented architectures, synthesis flows, and verification methodologies.

As a technical leader, you are adept at mentoring junior engineers, leading small teams, and ensuring design excellence through robust documentation and quality processes. You have a keen eye for detail, proven proficiency in synthesizable Verilog/System Verilog coding, and a deep understanding of design flows, including CDC analysis, static timing, and formal checking. Your collaborative spirit shines when working with global teams, and you communicate technical concepts with clarity and confidence, whether with colleagues or customers.

You are driven by innovation and continuous learning, always seeking to stay ahead in technology trends relevant to IP core development for Enterprise, Commercial, and Automotive applications. Your initiative, problem-solving skills, and ownership of deliverables make you a valued contributor in any project. You’re looking for an environment where your technical expertise, leadership, and passion for excellence will have a significant impact on next-generation silicon solutions.

What You’ll Be Doing:

• Architecting and designing state-of-the-art RTL for DesignWare IP cores, focusing on protocols such as UALink, Ethernet, DDR, PCIe, and USB.
• Creating and documenting detailed architecture and micro-architecture specifications for medium to high complexity design components.
• Performing individual contributor and technical lead responsibilities, including RTL coding, synthesis, CDC analysis, debugging, and test development.
• Collaborating with verification teams on test planning, coverage planning, and verification closure to ensure high-quality deliverables.
• Interacting with customers to understand and translate specification requirements into robust design solutions.
• Mentoring and technically leading a team of designers, driving best practices and continuous improvement across global teams.

The Impact You Will Have:

• Deliver next-generation IP cores for high-performance applications in Enterprise, Commercial, and Automotive sectors.
• Advance Synopsys’ leadership in ultra-fast accelerator link and Ethernet technology through innovative design and architecture.
• Ensure robust, scalable, and high-quality ASIC designs that meet and exceed customer requirements.
• Facilitate cross-functional collaboration, driving design efficiency and verification excellence in multi-site teams.
• Contribute to the successful adoption of Synopsys IP by leading customers worldwide, enabling breakthrough silicon solutions.
• Enhance team expertise through mentorship, technical guidance, and fostering a culture of innovation and continuous learning.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) with 12+ years of relevant ASIC design experience.
• Expertise in protocols such as UALink, Ethernet, DDR, PCIe, USB, and hands-on experience with control path-oriented designs (e.g., asynchronous FIFO, DMA, RAM interfaces).
• Proficiency in synthesizable Verilog/System Verilog RTL coding, simulation, and design verification tools.
• Strong background in lint, CDC, synthesis, static timing analysis, formal checking, and P&R-aware synthesis flows (Fusion Compiler experience is a plus).
• Experience with revision control systems (Perforce or similar), scripting languages (Perl/Shell), and exposure to IP design quality processes.

Who You Are:

• Innovative problem-solver with a proactive approach and strong initiative.
• Excellent communicator, able to bridge technical details with team members and customers.
• Collaborative team player, thriving in diverse, global environments.
• Mentor and leader, passionate about developing talent and sharing knowledge.
• Detail-oriented professional committed to delivering high-quality, reliable solutions.

The Team You’ll Be A Part Of:

You’ll join the DesignWare IP Design R&D team at Synopsys’ Bangalore Design Center, collaborating with expert engineers across multiple global sites. The team is dedicated to developing high-performance IP cores for a broad range of applications, emphasizing technical excellence, innovation, and quality. You will work in an environment that encourages learning, growth, and leadership, contributing to products that shape the future of silicon design.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.