Principal RTL Design Engineer

Category Engineering Hire Type Employee Job ID 17050 Remote Eligible No Date Posted 05/06/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building RTL that ships in real silicon, not just passes verification. The difference between a design that meets PPA targets and one that gets re-spun is usually a microarchitecture decision made early, and you are the engineer who sees that tradeoff coming. You know how to sit with architects and translate system intent into implementable blocks that actually synthesize cleanly and close timing without heroics downstream.

Working across processor architectures like ARM, RISC-V, or x86 feels natural because you understand the fundamentals beneath the ISA. You have debugged enough CDC violations and timing paths to know when a problem is tooling and when it is your logic. Scripting in Python or Perl is how you move faster and catch issues before they hit verification. At Synopsys, you will work on next-generation IP and processor subsystems where your decisions shape products that power everything from automotive systems to AI accelerators.

What You'll Be Doing

• Collaborate with architects to define microarchitecture and hardware specifications for processor blocks and subsystems
• Develop synthesizable RTL in Verilog and SystemVerilog with explicit focus on power, performance, and area tradeoffs
• Run linting, CDC, RDC checks using Spyglass and VCLP, then drive synthesis and timing closure with Design Compiler and PrimeTime
• Review verification test plans, define coverage and sign-off criteria, and ensure your blocks meet functional targets
• Work with DFT, physical design, and prototyping teams to ensure clean integration and meet downstream constraints
• Write automation scripts in Python or Perl to streamline design checks and handoff processes

The Impact You Will Have

• Your microarchitecture decisions will directly influence the performance and power profile of next-generation Synopsys IP
• The RTL you write will go into tape-outs that power automotive, AI, and high-performance computing systems worldwide
• Your collaboration with verification will reduce bring-up time and increase first-pass success rates
• The design quality you bring will reduce downstream respins and accelerate time to market
• Your scripting and automation will improve design productivity and catch issues earlier in the flow

What You'll Need

• BTech or MTech in Electrical or Electronics Engineering
• 6+ years of hands-on experience in ASIC or SoC design with RTL development and tape-out delivery
• Deep expertise in Verilog and SystemVerilog, with working knowledge of UPF and clock gating techniques
• Proven experience with Spyglass, VCLP, Design Compiler, and PrimeTime in real design flows
• Solid understanding of at least one processor architecture such as ARM, RISC-V, x86, or MIPS
• Hands-on scripting ability in Python or Perl to automate checks and manage design data

Who You Are

• You can walk into an architecture review and leave with a block-level spec that is implementable and meets PPA goals
• When a timing path fails, you trace it back to the logic and decide if the microarchitecture needs to change
• You write RTL that verification engineers can actually work with, clear intent, good naming, no hidden assumptions
• Debugging a CDC violation or synthesis mismatch does not frustrate you, you know how to isolate root cause
• You communicate clearly across functions, whether explaining a design tradeoff or flagging a DFT concern

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.