Scientist- ASIC Verification, Interface IP- PCIe/CXL

Category Engineering Hire Type Employee Job ID 17955 Remote Eligible No Date Posted 06/18/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent the better part of a decade building verification environments that have to catch the bugs no one else sees, the corner cases buried three layers deep in protocol state machines, the timing violations that only surface when five things go wrong at once. You know that verifying a PCIe or CXL controller is not about running regressions, it is about building testbenches that think like attackers and corner cases like reality.

When you look at a protocol spec, you see the gaps, the ambiguities, the places where two features will collide in silicon. You have built UVM environments from scratch, debugged waveforms at 3 a.m., and shipped controllers that actually work in production systems. You do not wait for a verification plan to be perfect, you write it, refine it as you learn, and bring the team along with you.

Mentorship is not a side responsibility for you, it is how you scale impact. You have taught engineers how to think about coverage, how to debug smarter, and how to build testbenches that last beyond one project. At Synopsys, you will shape how Interface IP gets verified across one of the most critical product lines in the semiconductor industry.

What You'll Be Doing

• Define and architect RTL verification strategies for Synopsys Interface IP controllers, with a focus on PCIe, CXL, and UCIe protocols at both block and chip integration levels
• Build and own testbench architectures using UVM and advanced verification methodologies that scale across multiple protocol variants and product generations
• Develop comprehensive verification plans that map protocol specifications to coverage models, corner cases, and real-world system interactions
• Work directly with design, architecture, and product teams to align verification strategy with product roadmaps and customer requirements
• Debug complex protocol interactions, trace signal-level failures through multi-layer testbenches, and root-cause issues that span RTL, testbench, and tooling
• Mentor verification engineers across the team, reviewing test plans, guiding debug sessions, and establishing best practices that raise the bar for the entire group
• Collaborate with cross-functional teams in the U.S., Europe, and Asia to ensure verification quality and consistency across global development efforts

The Impact You Will Have

• Directly improve the reliability and time-to-market of Synopsys Interface IP controllers that power data center, AI, and automotive silicon across the industry
• Establish verification methodologies and testbench frameworks that become the foundation for future protocol IP development at Synopsys
• Reduce post-silicon bugs and customer escalations by catching critical issues earlier in the verification cycle through smarter coverage and corner case modeling
• Build a stronger, more capable verification team by mentoring engineers and spreading deep protocol knowledge across the organization
• Influence product and architecture decisions by surfacing verification insights that shape how controllers are designed and validated
• Help Synopsys maintain its leadership position in Interface IP by ensuring every release meets the quality bar that customers depend on
• Shape the strategic direction of verification tooling, flows, and infrastructure used across the IP division

What You'll Need

• 20+ years of hands-on experience in ASIC RTL verification, with a strong track record of shipping complex digital designs
• Deep expertise in PCIe (Gen 3 through Gen 6), CXL (1.x, 2.0, or 3.0), or UCIe protocol verification, including knowledge of link training, error handling, and system-level interactions
• Proven ability to define and execute testbench architecture using SystemVerilog, UVM, and constrained-random verification techniques
• Strong command of verification planning, coverage modeling, assertion-based verification, and formal methods
• Experience working independently at an architect or technical lead level, driving verification strategy with minimal oversight
• Demonstrated ability to mentor engineers and lead technical discussions across global, cross-functional teams
• Excellent written and verbal communication skills, with the ability to explain complex verification tradeoffs to architects, designers, and product managers

Who You Are

• You can walk into a design review, spot a verification gap in the architecture, and articulate the risk in a way that gets the team to act
• When a regression fails at 2 a.m. before tapeout, you are the person who stays, finds the root cause, and documents it so it never happens again
• You do not just run coverage reports, you read them critically and know when 100% coverage still means you are missing something
• Mentoring is not about telling people what to do, it is about asking the right questions so they learn to debug and think like you do
• You have strong opinions on verification methodology, but you listen when someone has a better idea and you change your mind when the data says you should
• You treat verification like a product, with users (the design team), a roadmap (the verification plan), and a quality bar that you own end to end

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.