Senior Verification Engineer

Category Engineering Hire Type Employee Job ID 17842 Remote Eligible No Date Posted 06/16/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years verifying designs that cannot afford to fail, where a missed corner case does not just break a testbench, it breaks a product roadmap. You know that verification is not about running tests, it is about finding the one scenario no one thought to write down, the edge case that only shows up when three things happen at once. You think in coverage metrics, but you also think in risk. You can look at a spec and see what is missing before the first line of SystemVerilog gets written.

Mixed-signal work does not scare you. You understand that the digital logic you verify lives next to analog blocks that behave differently under PVT corners, and you have learned to build testbenches that respect that reality. You have worked with protocols like DDR or HBM, or you are hungry to learn them because you know that high-speed interfaces are where the hardest verification problems live.

You do not wait for perfect documentation. You ask the right questions, build the environment, and start closing coverage while others are still debating the plan. At Synopsys, you will work on memory interface IP that powers AI and high-performance computing systems used across the industry.

What You'll Be Doing

• Write verification specifications and test plans for next-generation DDR and HBM memory interface IP, translating design intent into executable verification strategy
• Design and build SystemVerilog testbenches and UVM environments that verify complex mixed-signal ASIC designs across functional, performance, and corner case scenarios;
• Develop and execute test cases targeting protocol compliance, signal integrity, timing closure, and power-aware verification for high-speed interfaces;
• Create and maintain behavioral models in Verilog and SystemVerilog to enable early verification before RTL freeze;
• Drive coverage closure using functional, code, and assertion-based metrics, identifying gaps and writing directed tests to hit hard-to-reach scenarios;
• Debug failures across digital and mixed-signal domains, working closely with design engineers to root-cause issues in simulation and on test silicon;
• Document verification environments, methodologies, and results for internal use and customer delivery;

The Impact You Will Have

• Enable Synopsys to deliver memory interface IP that meets the performance and reliability requirements of AI accelerators, data centers, and high-performance computing systems;
• Reduce post-silicon debug cycles by catching critical issues in verification, saving months of schedule and engineering effort;
• Build reusable verification IP and environments that accelerate future product development across the memory interface portfolio;
• Influence design decisions early by identifying verification challenges and architectural risks before tape-out;
• Mentor and guide junior verification engineers, raising the technical bar across the team;
• Contribute to the adoption of advanced verification methodologies like formal verification and AI-driven test generation within the team;
• Help Synopsys maintain its leadership position in memory IP by ensuring every release meets the highest quality standards

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field;
• 5+ years of hands-on verification experience in ASIC or mixed-signal design environments;
• Deep expertise in SystemVerilog and UVM methodology, with proven ability to build complex testbenches from scratch;
• Strong understanding of Verilog for RTL analysis and behavioral modeling;
• Proficiency in scripting languages such as Python, Perl, or Tcl for automation and test infrastructure development;
• Experience working in Unix/Linux environments and using industry-standard EDA tools for simulation and debug;
• Knowledge of high-speed interface protocols such as DDR, HBM, or DFI is a strong plus, as is experience with formal verification tools.

The Team You'll Be Part Of

You will join a highly experienced ASIC mixed-signal design and verification team in Porto, working on current and next-generation DRAM interface products including DDR and HBM. The team applies AI and advanced algorithms to solve complex design and verification challenges, and you will collaborate closely with digital and mixed-signal engineers across the full product lifecycle, from specification development through test-chip bring-up and validation. This is a team that values technical depth, and you will have the opportunity to work with senior engineers who have been building memory IP for years.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.