Logic Design Architect

Category Engineering Hire Type Employee Job ID 9265 Base Salary Range $181000-$271000 Remote Eligible No Date Posted 16/10/2025

We Are:   Preferring to make this hire in Boxborough, Sunnyvale, Oregon or in Austin. 

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

A seasoned Logic Design Engineer passionate about high-performance digital design, with deep experience in SerDes, DDR/HBM, or Die-to-Die PHY logic. You excel in cross-functional collaboration, have strong skills in PHY IP and SOC RTL design and verification, and communicate technical concepts clearly. You thrive on learning new technologies and mentoring others.

What You’ll Be Doing:

• Designing high-speed Die-to-Die interconnect IP.
• Collaborating with teams to define best-in-class IP designs.
• Optimizing designs for performance, power, and area.
• Participating in the full design cycle and supporting silicon/customer needs.
• Leading design reviews and mentoring engineers.
• Staying current with industry trends.

The Impact You Will Have:

• Driving development of world-class Die-to-Die IPs.
• Shaping next-generation semiconductor technologies.
• Delivering quality IP for SOC/SIP solutions.
• Enhancing product adoption through technical expertise.
• Mentoring engineers and fostering learning.
• Strengthening Synopsys’ industry leadership.

What You’ll Need:

• BSEE with 15+ years direct industry experience in SerDes, DDR/HBM, or UCIe PHY architecture.
• Expertise in Hard IP design.
• System Verilog and RTL-to-gate design skills.
• Full IP/SOC design cycle knowledge.
• Strong problem-solving and communication skills.

Who You Are:

• Independent, proactive, and collaborative.
• Clear communicator and effective mentor.
• Continuous learner and team player.

The Team You’ll Be A Part Of:

Join a talented, innovative team developing high-performance digital designs for PHY, DDRIO, and UCIe PHY logic. We value teamwork, learning, and excellence.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.