ASIC Digital Design/Verification, Senior Engineer

ASIC Digital Design/Verification, Senior Engineer

Seeking a highly motivated and innovative experience digital design engineer with knowledge of ASIC development, modeling, and digital signal processing. Strong theoretical and practical background in high-speed serializer and data recovery circuits is an asset. The position offers an excellent opportunity to work with an experienced team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs (PAM4- and NRZ-based SerDes PHY products), from specification development to performing functional and performance tests on the test-chips.

Key Qualifications

• Relevant ASIC digital design experience in the industry.
• Strong scripting expertise in Shell, Perl, Python etc. language.
• Good understanding of digital signal processing is a plus.
• Good theoretical and/or practical understanding of components in high-speed SerDes PHY, such as CDR, ADC, FracN PLL etc., is an important asset.
• Experience with block-level and system-level modeling using with either Matlab, Simulink, Verilog or System Verilog
• BSEE or MSEE plus a minimum of 3+ years of digital design and verification experience in the industry
• Good organization and communication skills for interacting between different design groups and/or customers.

Knowledge of the following will be considered as an important asset:

• High-speed digital & mixed-signal ASIC design
• Experience in analog design

Unique about this Position

• You will gain industry leading-edge knowledge while interacting closely with many veterans in cross-functional domains.
• Your work will have an impact on our next-generation flagship product architecture, quality, and customer engagement.