ASIC Digital Design, Sr Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly motivated and detail-oriented professional with a passion for digital and mixed signal verification. You thrive in collaborative environments and have a proven track record of learning and applying new technologies. Your strong analytical and problem-solving skills enable you to tackle complex verification challenges effectively. You have excellent communication skills and can articulate technical concepts clearly to both technical and non-technical audiences. You possess a solid understanding of Verilog and SystemVerilog, as well as experience with scripting languages. Your previous work with CAD tools and high-speed interface protocols like HBM, DDR, and DFI sets you apart. Additionally, you are familiar with verification methodologies such as UVM, making you an asset to any verification team.

What You’ll Be Doing:

• Generating verification specifications for mixed signal (digital and analog) designs.
• Designing and implementing test benches and test cases to ensure thorough verification coverage.
• Evaluating and exercising various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, and constraint development.
• Developing and maintaining documentation for test plans, verification environments, and usage guidelines.
• Participating in the evaluation and troubleshooting of digital and mixed signal designs to ensure functionality and performance.
• Collaborating with global teams to define and refine verification strategies and methodologies.

The Impact You Will Have:

• Ensuring the reliability and performance of Synopsys' mixed signal IP products.
• Contributing to the development of cutting-edge technologies that power the Era of Smart Everything.
• Reducing verification cycle times and improving overall product quality.
• Helping to bring differentiated products to market quickly with reduced risk.
• Enhancing the verification process through innovative test bench designs and methodologies.
• Supporting the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements.

What You’ll Need:

• Proven desire to learn and explore new technologies.
• Strong communication skills in English.
• Excellent analysis and problem-solving skills.
• Prior experience with CAD tools for development.
• Knowledge of Verilog and SystemVerilog.
• Experience with scripting languages.

Who You Are:

• A collaborative team player who thrives in a global, diverse work environment.
• A proactive individual with a keen attention to detail.
• An effective communicator who can convey complex technical concepts clearly.
• An innovative thinker who is always looking for ways to improve processes and outcomes.
• A problem solver who enjoys tackling new challenges and finding creative solutions.

The Team You’ll Be A Part Of:

You will be part of the Synopsys mixed signal IP team, working alongside talented engineers from around the world. Our team is focused on developing and verifying high-performance mixed signal designs that drive the innovations of tomorrow. We collaborate closely with other teams within Synopsys to deliver comprehensive solutions that meet the evolving needs of our customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.