ASIC Digital Design Engineer
Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
Job Description
ASIC Digital Design Engineer
Synopsys, a world leader in the Semiconductor IP industry, is seeking a Mixed Signal Verification Engineer whose mandate is to:
- Work in a Digital and Verification Development team contributing to the development and validation of complex digital mixed signals for high-speed interface IP
- Understand the IP from a System level, Analog and Digital
- Understand ASIC design Flow
- Engage in verification activities under supervision of more experienced personnel, and to exercise judgment to determine appropriate actions to achieve the required specifications.
- Assembling and implementing Subsystem RTL / constraints and DFT architecture for internal subsystems.
- Has a good understanding of the implementation flows and methodologies for deep sub-micron designs
- Prepare and present reports outlining the outcome of technical projects.
- Has expertise in Verilog RTL coding, Lint/CDC/RDC can be a bonus
- Build productive working relationships, with different teams, cross project
- Participate in applicable product/project reviews
Key Qualifications
- University master’s degree in electronic/Micro-electronics engineering
- Knowledge of IC design flows
- Digital design knowledge
- Digital tools understanding
- Willingness to learn new things.
- Good team-player
- Organizational skills are essential.
- Good problem-solving skills
- Digital signal processing essential
- Digital Logic understanding
- Good English communication skills
Preferred Experience
- 2+ years of relevant experience is highly preferred
- Experience in producing high-quality technical documentation is desirable
- Experience with analog tools, preferable Synopsys tools
- Good understanding of analog design
- Experience in Verilog/VHDL
- Proficiency in at least on programming language such as Python, C, C++ and MATLAB
- Understating of in System Verilog /VMM/UVM
- Exposure to Unix, Perl and TCL scripting
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things(IOT). These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Synopsys' leading DesignWare IP portfolio is developed by an IP Design Team within Synopsys’ Solutions Group. Part of the Team is located in Lisbon and is staffed with analog and digital IC design engineers, application engineers and test engineers among others. The company's extensive IP portfolio enables next-generation SoC designers to integrate silicon-proven functionality previously available only to large integrated device manufacturers. The IP is licensed to leading semiconductor companies across all major markets, offering high-precision, single-function blocks to complete interface sub-systems.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
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Time Away
In addition to company holidays, we have ETO and FTO Programs.
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Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
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Retirement Plans
Save for your future with our retirement plans that vary by region and country.
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Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
Hiring Journey at Synopsys
Find the open role that’s
right for you
- ASIC Digital Verification, Principal Engineer Bengaluru, India
- EMEA People Shared Services Manager Porto Salvo, Portugal
- R&D Engineering, Staff Engineer - VIP Verification Delhi, India
- ASIC Digital Design, Sr Engineer Wuhan, China
View all job opportunities here
View all job opportunities here
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