ASIC Digital Verification Engr

About Synopsys

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. Smart medical devices. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. Synopsys is committed to fostering an environment that treats people with respect, honesty, and professionalism. We’re also committed to partnering with the communities in which we work. Every year, Synopsys reaches out to local communities with resources and employee leadership to support education, science programs and a variety of other activities. Come and be part of a collaborative team environment that innovates and shapes the way the world moves on.

ASIC Digital Verification Engr

Seeking a highly motivated and innovative ASIC Digital Verification engineer. The candidate would be working as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation of USB/PCIe/DPHY/CDPHY/MPHY/DisplayPort/HDMI/SATA/Ethernet products for mobile phones, automotive industry, drones, IoT, and other consumer markets.

The PHY development is very dynamic and provides an endless list of challenges. The candidate would have an initial training done by the top experts in the field as well as continuous on the job training and assignments. The work is very challenging, not only given the constant technological changes but also to the need of find new solutions to the new state of art problems.

Main duties might include:

• Work in a Digital and Verification R&D team contributing to the development and validation of complex digital mixed-signal circuits for high-speed interface IP.
• Define, develop, and support complex verification environments using latest standards methodologies: System Verilog, UVM and Formal verification.
• Contribute to meet verification coverage (functional and code) metrics targets.
• Create verification test plan, verification environment documentation and test environment usage documentation.
• Review SerDes standards and architecture documents to develop verification sub-block specifications.
• Perform RTL and gate-level simulations of circuits, interpret the results and optimize the design until the predetermined functionality and timing is satisfied.
• Participate in the behavioral modeling activities using Verilog/SystemVerilog language.
• Identify design problems, possible corrective actions and/or inconsistencies on documented functionality of digital and mixed-signal circuits.
• Work towards improving efficiency in design/verification procedures and methodologies.
• Other related duties as assigned by the upper manager.

Development opportunities:

• Develop systematic ways to address new problems, think outside of the box.
• Produce high quality work and products.
• Have an impact on the new product architectures, quality, and development strategies.
• Write patents for any inventions.

Minimum Requirements:

• University degree in electronics engineering, computer science or similar.
• Experience in producing good technical documentation.
• Good communication and organizational skills.
• Good knowledge of both written and spoken English.
• Willingness to learn new things.
• Demonstrate good problem-solving skills.
• Proficiency in at least on programming language such as Python, Perl, C, C++ or MatLab.
• Understanding of IC design flows and analog circuit design would be advantageous.
• Understanding of Verilog/System Verilog language would be advantageous.
• Understanding of a verification methodology such as UVM is a plus.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.