Layout Design, Sr Engineer

About Synopsys:
Synopsys technology is at the heart of innovations that are changing the way people work and play. Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere. These breakthroughs are ushering in the era of Smart Everything―where devices are getting smarter and connected, and security is an integral part of the design.

Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high performance multi-rate transceiver portfolio for high-end networking and high performance computing applications. The area-efficient PHY provides a low active and standby power solution that supports multiple electrical standards, including PCI Express® (PCIe®) 6.0, 1G to 112Gbps electrical PHY for 400G/800G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), Compute Express Link (CXL), JESD204C, CPRI, SATA, and other industry-standard interconnect protocols. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 112G PHY delivers signal integrity and jitter performance that exceeds the standards electrical specifications.

Job Description:

As a part of our team you will be responsible for delivering fully-verified, clean layout. This includes the following: - Crafting sophisticated layout for mixed signal and analog circuits in deep sub-micron CMOS technologies. - Reviewing and analyzing floorplans and intricate circuits with circuit designers. - Running complete sets of design verification tools available on AMS blocks. - Working with the circuit design team to plan/schedule work and coordinate vital layout tradeoffs as needed. - Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. - Exceeding engineering specifications and expectations by working closely with the circuit design team. - Applying sophisticated CAD tools and mask design knowledge to deliver accurate and robust layout that matches performance, area and power requirements.

• Requirements :
• B.Tech/M.Tech with  1-3 years of relevant experience
•  Proven experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits
•  Experience in implementing analog layouts to achieve tight matching, low noise, and low power consumption. Layouts may include data converters, PLLs, analog blocks, resistors, capacitors, pad IOs, ESD structures, etc.
•  High level of proficiency in custom and standard cell based floor-planning and hierarchical layout assembly.
•  Must understand techniques for leading IR drop, RC delay, electro-migration, self heating and coupling capacitance.
•  Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard methodologies, and proactively work with circuit designer to identify the best approach to solving problems.
•  Deep proficiency in interpretation of DRC, ERC, LVS, etc. reports.
•  Excellent communication skills and able to work with multi-functional teams.