Synopsys' high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted Synopsys' latest PCIE GEN6/GEN7 with CXL/IDE improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU. If you are interested in joining us and contributing to the rapid development of the industry, maybe youare the one we are looking for.

We’re looking for an IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer to join the team.  

Key qualifications:

• Minimum5+ years Bacheloror 3+ years Masterof IP/ASIC/SOCDesignImplementation experiencerequired.
• Hands-on experience in synthesis, timingoptimization,SDC writing, CDC/RDC checking,etc. 
• Domainunderstandingoneoftheinterface standards: PCIe, USB,Display Port,Ethernet, or DDR.
• Good communicationskills while interacting with internal teams and customers.

Preferred Experience:

• Experience in Design Compiler, Fusion Compiler,PrimeTime,Spyglassor VC Spyglass
• Experience inDesignWareCoreIPs or PHYs
• Experience in TCL, Perl, Python, or other shell scripting