ASIC Digital Design, Principal Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced ASIC Digital Design, Principal Engineer with a deep passion for developing cutting-edge technology. With over 15 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of Verilog RTL, verification processes, and ASIC design flows. Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.

What You’ll Be Doing:

• Develop a complete front-to-back flow (RTL generation, simulation, synthesis & implementation) in the Synopsys coreAssembler tool for PHY and Controller subsystems.
• Build a reference subsystem in the coreAssembler flow and assist IP development teams with the flow.
• Evaluate and exercise various aspects of the development flow, including RTL lint and CDC checking, functional simulation, constraint checking, design for test logic, synthesis, timing analysis, power analysis, and verification coverage.
• Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.
• Work as a liaison between EDAG tool and IP design teams.
• Continuously improve and refine design processes to enhance efficiency and performance.

The Impact You Will Have:

• Drive innovation in high-speed digital IP core and Subsystem development.
• Enhance the efficiency and effectiveness of our design and verification processes.
• Contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems.
• Ensure the highest quality standards in the design and implementation of our products.
• Facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence.
• Support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.

What You’ll Need:

• BS or MS in Electrical Engineering with 15+ years of experience in high-speed digital IP cores and/or SOCs development.
• Proficiency in Verilog RTL, verification processes, and ASIC design flows and tools.
• Experience with memories, logic libraries, and PDK versions.
• Strong analytical and problem-solving skills.
• Excellent written and verbal communication skills, with an ability to create clear and concise documentation.
• Familiarity with Synopsys tools (SpyGlass, VC Static, Fusion Compiler, Formality, PrimeTime, coreTools) is a plus.
• Knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

Who You Are:

You are a collaborative and innovative engineer with a strong technical background and a passion for excellence. You thrive in a dynamic environment and enjoy working with global teams to achieve common goals. Your ability to communicate effectively and your commitment to continuous improvement make you an invaluable asset to our team.

The Team You’ll Be A Part Of:

You will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.