Principal Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly motivated and innovative ASIC digital verification engineer with a passion for technology and a proven track record in the field. You thrive in a collaborative environment, working alongside a team of experienced mixed-signal design engineers. You have a strong background in digital verification methodologies such as VMM and UVM, and you are proficient in writing test cases in Verilog and System Verilog. Your solid understanding of digital circuit design, combined with your basic knowledge of C/C++ and RISC processors, makes you an invaluable asset to our team. You are a self-learner who can work independently, and you possess excellent organizational and communication skills. Your familiarity with scripting languages like Python or Perl further enhances your ability to contribute to our projects. You are eager to take on new challenges and play a critical role in verifying current and next-generation Backplane Ethernet, PCIe, SATA, and USB SERDES products.

What You’ll Be Doing:

• Creating and updating test plans and test cases
• Writing modular constrained-random/coverage driven Verilog, System Verilog, and UVM/VMM testbenches
• Writing System Verilog assertions and models
• Monitoring simulation regressions and debugging RTL and Gate level simulation failures
• Writing functional coverage and performing functional/code/assertion coverage analysis
• Tracking and reporting issues in Jira and documenting in Confluence
• Code behavioral models with RNM (Real Number Modelling)

The Impact You Will Have:

• Ensure the functionality and performance of our advanced mixed-signal designs
• Contribute to the development of high-end mixed-signal products
• Help reduce risk and accelerate time-to-market for differentiated products
• Enhance the reliability and efficiency of our verification processes
• Support the integration of more capabilities into SoCs
• Drive innovation in the Era of Smart Everything

What You’ll Need:

• BS/MS in Electronics / Electrical Engineering or related fields with 5+ years of industry experience with digital verification methodology such as VMM/UVM
• PCIe PHY experience required
• Solid experience in writing test cases in Verilog and System Verilog
• Solid experience in debugging complex testbench and design-related issues
• Solid understanding of digital circuit design
• Basic understanding of C/C++ and RISC processors
• Familiarity with scripting languages (Python or Perl)
• Self-learner/independent, with good organizational and communication skills

Who You Are:

• Knowledgeable in high-speed digital & mixed-signal design
• Experienced with System Verilog Assertions / formal verification
• Organized and an effective communicator
• Innovative and able to work independently
• Collaborative and team-oriented

The Team You’ll Be A Part Of:

You will be part of a highly experienced mixed-signal design team responsible for delivering high-end mixed-signal designs. Our team is dedicated to verifying current and next-generation Backplane Ethernet, PCIe, SATA, and USB SERDES products, ensuring their functionality and performance. Together, we work on creating test plans, developing verification environments, and performing functional and performance tests on the test-chips/products.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.