ASIC Digital Design, Staff Engineer

Category Engineering Hire Type Employee Job ID 16962 Remote Eligible No Date Posted 06/03/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years designing RTL that ships in silicon, not just passes simulation. You know that a clean architecture today saves weeks of debug three months from now, and you are the kind of engineer who thinks through corner cases before they become customer escalations. You are comfortable working in Verilog and SystemVerilog across complex IP blocks, and you treat testbench development as seriously as the design itself.

You do not need a perfect spec to get started. You ask the right questions, clarify ambiguity with architects and verification teams, and move forward with confidence. When something breaks, you dig in, whether that means tracing signals through waveforms or working directly with a customer to reproduce an issue in their environment. At Synopsys, you will work on IP that goes into the most advanced chips being built today.

What You'll Be Doing

• Design and implement RTL for Silicon Lifecycle Management IP blocks, including monitoring, security, and telemetry features for next-generation 3D-IC architectures
• Develop directed and constrained-random test cases in SystemVerilog to validate functionality, performance, and edge case behavior
• Debug complex issues across the design stack, working with waveforms, synthesis tools, formal verification, and customer-reported scenarios
• Collaborate with verification, physical design, and architecture teams to ensure your RTL meets timing, area, and power targets
• Work directly with customers and field application engineers to reproduce, diagnose, and resolve issues in production environments
• Participate in code reviews and technical discussions, providing feedback and ensuring design quality across the team

The Impact You Will Have

• Deliver RTL that powers SLM IP used by leading semiconductor companies in high-volume production chips
• Reduce time to market for customers by designing IP blocks that integrate cleanly and perform reliably across process nodes
• Improve product quality by catching issues early through rigorous testbench development and formal verification
• Strengthen customer relationships by providing responsive, technically sound support during integration and debug
• Influence the architecture and roadmap of next-generation 3D-IC and SLM solutions through technical contributions
• Contribute to a culture of technical excellence where design decisions balance short-term delivery with long-term maintainability

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
• 4+ years of hands-on experience designing and verifying RTL in Verilog or SystemVerilog for ASIC or FPGA projects
• Proficiency with industry-standard EDA tools for simulation, synthesis, and static timing analysis
• Experience writing TCL scripts to automate design flows, run regressions, or configure toolchains
• Solid understanding of formal verification methodologies and where they fit in the verification plan
• Comfortable working in Unix or Linux environments for development, scripting, and tool execution
• Strong written and verbal communication skills in English for documentation and cross-functional collaboration

Who You Are

• You can explain a design tradeoff to an architect in two sentences without losing the technical nuance
• You treat debugging like a puzzle, methodically isolating root causes and documenting what you find so the team does not hit the same issue twice
• You push back when a specification is incomplete or a testbench does not cover the right scenarios
• You are organized enough to manage multiple design blocks, customer issues, and code reviews at once without dropping threads
• You stay current with industry trends because you are genuinely curious about where silicon design is headed

The Team You'll Be Part Of

You will join a global engineering team focused on Silicon Lifecycle Management IP, working on next-generation 3D-IC projects that address monitoring, security, and telemetry challenges in advanced semiconductor designs. The team collaborates closely with architecture, verification, physical design, and customer-facing engineers across multiple time zones.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.