Validation/Verification methodologies (UVM, simulation, SVA), Staff Engineer
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years in verification, closing coverage on complex IP and SoC designs, and you know that the hardest part is not writing the tests but knowing when you are actually done. You understand the difference between hitting a metric and truly verifying a design, and you have debugged enough corner cases to recognize when something does not add up, whether it came from a human or an AI.
You are curious about how AI can change verification work, not because it is trendy but because you have seen the manual grind of coverage closure and you want better tools. You do not blindly trust AI outputs. You validate them, push back when they miss the mark, and help refine the systems so they get smarter. You think of AI as a coworker you are training, not a magic box.
You care about knowledge quality. You have seen what happens when verification artifacts are poorly documented or inconsistently tagged, and you take ownership of making sure the information you create can actually be reused. At Synopsys, you will work on verification workflows that are being transformed by AI, and what you validate, curate, and teach will shape how the next generation of verification gets done.
What You'll Be Doing
- Drive end-to-end verification closure on complex IP and SoC designs, including functional, code, and scenario coverage using UVM, SystemVerilog Assertions, and simulation tools like VCS and Verdi
- Define coverage strategies, identify gaps, and use AI-assisted tools to accelerate test generation, debug, and convergence while independently validating all outputs for correctness
- Collaborate with AI agents and tools for testbench generation, coverage analysis, debug assistance, and report generation, actively evaluating and refining what they produce
- Own the quality and structure of verification artifacts, ensuring test plans, debug logs, and reports are well-tagged, contextualized, and consumable by AI systems
- Provide structured feedback to AI and tool development teams to improve model accuracy, usability, and trustworthiness in verification workflows
- Pilot and benchmark AI-based verification solutions, measuring their impact on productivity, quality, and coverage closure timelines
- Contribute to building self-improving knowledge systems that evolve with verification data and enable scalable reuse across global teams
The Impact You Will Have
- Accelerate coverage closure cycles and reduce time to signoff by integrating AI-assisted methodologies into verification workflows
- Increase trust and adoption of AI tools across verification teams by validating outputs and demonstrating where they add real value
- Improve the quality and completeness of verification outcomes through domain-driven insights and rigorous validation practices
- Enable scalable, reusable knowledge systems that enhance organizational learning and reduce redundant work across projects
- Help shape the transition to agentic, autonomous verification ecosystems by defining what good AI collaboration looks like in practice
- Influence verification strategy and tooling decisions across Synopsys by benchmarking current practices against industry standards and emerging AI capabilities
- Build a foundation for continuous improvement where verification data, feedback, and AI capabilities create a flywheel of increasing effectiveness
What You'll Need
- Bachelor's degree in Electronics with 2+ years of verification experience, or Master's degree in Electronics with 1+ year of verification experience
- Proven expertise in verification methodologies including UVM, simulation, and SystemVerilog Assertions, with a track record of driving coverage closure on complex designs
- Strong understanding of digital design fundamentals using Verilog, VHDL, or SystemVerilog, and experience working in complex SoC or IP verification environments
- Hands-on experience with EDA tools such as VCS and Verdi, and proficiency in scripting with Python, TCL, or UNIX-based workflows
- Ability to critically evaluate AI-generated outputs, identify accuracy gaps and edge cases, and provide actionable feedback to improve AI systems
- Experience or strong interest in AI/ML-assisted verification workflows, automation, and data-driven decision making is a plus
- Strong debugging and analytical skills with the ability to work across global teams and communicate complex verification issues clearly
Who You Are
- You take ownership of coverage closure and do not call something done until you have validated it from multiple angles, whether the output came from a simulation or an AI tool
- You can look at an AI-generated test or summary, spot what it missed, and articulate exactly why it matters in terms a tool team or a manager can act on
- You are detail-oriented with high standards for quality, and you get frustrated when verification artifacts are sloppy or inconsistent because you know it creates problems downstream
- You are proactive about exploring new workflows and technologies, and comfortable working in environments where the tools and processes are still being figured out
- You think like a knowledge builder, not just a task executor, always asking how the work you are doing today can make the next project easier
- You are comfortable in a rapidly evolving, AI-first environment where the rules are not all written yet and your input will help shape what comes next
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
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